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Integrated Circuit Systems, Inc.
ICS9250-10
Preliminary Product Preview
Frequency Timing Generator for Pentium II Systems
General Description
The ICS9250-10 is a single chip clock for Intel Pentium II. It provides all necessary clock signals for such a system. Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces EMI by 8dB to 10 dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9250-10 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations.
Features
Generates the following system clocks: - 3 CPU (2.5V) 66.6/100 MHz (up to 133MHz through I2C selection) - 9 SDRAM (3.3V) up to 133MHz - 8 PCI (3.3 V) @33.3MHz - 2 IOAPIC (2.5V) @16.67 or 33.3MHz - 2 Hublink clocks (3.3 V) @ 66.6 MHz - 2 USB (3.3V) @ 48 MHz ( Non spread spectrum) - 1 REF (3.3V) @ 14.318 MHz Supports spread spectrum modulation , down spread 0 to -0.5% I2C support for power management Efficient power management scheme through PD# Uses external 14.138 MHz crystal

Block Diagram
Pin Configuration
56-Pin 300 mil SSOP
*60K ohm pull-up to VDD on indicated inputs.
Power Groups
VDD0, GND0 = REF & Crystal VDD1, GND1 = 3V66 [1:0] VDD2, GND2 = PCICLK[7:0] VDD3, GND3 = PLL core VDD4, GND4 = 48MHz [1:0] VDD5, GND5 = SDRAM_F, SDRAM [7:0] VDDL0, GNDL0 = CPUCLK [2:0] VDDL1, GNDL1 = IOAPIC [1:0]
PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.
Pentium II is a trademark of Intel Corporation I2C is a trademark of Philips Corporation
9250-10 Rev J 6/15/99
ICS9250-10
Preliminary Product Preview Pin Descriptions
PIN NUMBER P I N NA M E FREQ_APIC REF0 3 4 5, 6, 14, 17, 23, 24, 35, 41, 47 8, 7 X1 X2 GND (0:5) 3V66 [1:0] TYPE IN OUT IN OUT PWR OUT PWR OUT OUT IN IN IN IN OUT OUT PWR OUT PWR OUT DESCRIPTION Latched input at Power On. this determines the IOAPIC frequency. When a "0" is latched, IOAPIC Freq=16.67MHz When "1" is latched, IOAPIC Freq=33.3MHz This pin has a 60K internal pull-up. 3.3V, 14.318MHz reference clock output. Crystal input, has internal load cap (33pF) and feedback resistor from X2 Crystal output, nominally 14.318MHz. Has internal load cap (33pF) Ground pins for 3.3V supply 3 . 3 V F i xe d 6 6 M H z c l o c k o u t p u t s f o r H U B 3.3V power supply 3.3V PCI clock outputs, with Synchronous CPUCLKS 3 . 3 V F i xe d 4 8 M H z c l o c k o u t p u t s f o r U S B Function Select pins. Determines CPU frequency, all output functionality. Please refer to Functionality table on page 3. Data input for I2C serial input. Clock input of I2C input Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 3ms. 3.3V output running 100MHz. All SDRAM outputs can be turned off through I2C 3.3V free running 100MHz SDRAM not affected by I2C Ground for 2.5V power supply for CPU & APIC 2.5V Host bus clock output. 66MHz or 100MHz depending on FS (0:1) pins Refer page 3. 2.5V power suypply for CPU & IOAPIC 2.5V clock outputs running at 16.67MHz or 33.3MHz.
1
2, 9, 10, 21, VDD (0:5) 22, 27, 33, 38, 44 20,19,18,16, PCICLK[7:0] 15,13,12,11 25, 26 28, 29 30 31 32 48MHz (0:1) FS (0:1) SDATA SCLK PD#
36, 37, 39, 40, 42, SDRAM [7:0] 43, 45, 46 34 56,48 49,50,52 51, 53 54, 55 SDRAM_F GNDL [1:0] CPUCLK [2:0] VDDL (0:1) IOAPIC [1:0]
2
ICS9250-10
Preliminary Product Preview Functionality Table
FS1 0 0 1 1 FS0 0 1 0 1 CPU Hi-Z TCLK/2 66 MHz 100 MHz SDRAM Hi-Z TCLK/4 100 MHz 100 MHz 3V66 Hi-Z TCLK/4 66 MHz 66 MHz PCICLK Hi-Z TCLK/8 33 MHz 33MHz 48MHz Hi-Z TCLK/2 48 MHz 48 MHz REF0 Hi-Z TCLK 14.318MHz 14.318MHZ IOAPIC Hi-Z TCLK/16 16.67MHz 16.67MHz Notes Tristate Test Mode
Clock Enable Configuration
PD# 0 1 CPUCLK LOW ON SDRAM LOW ON IOAPIC LOW ON 66MHz LOW ON PCICLK LOW ON REF, 48MHz LOW ON Osc OFF ON VCOs OF F ON
Select Functions
FS1 0 0 1 1 FS0 0 1 0 1 Tristate Test Mode Active CPU = 66MHz Active CPU = 100MHz Notes
3
ICS9250-10
Preliminary Product Preview
Power Down Waveform
Note
1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all the output clocks are driven Low on their next High to Low tranistiion. 2. Power-up latency <3ms. 3. Waveform shown for 100MHz
Maximum Allowed Current
810E Condition Powerdown Mode (PWRDWN# = 0 Full Active 66MHz SEL1, 0 = 10 Full Active 100MHz SEL1, 0 = 11 Max 2.5V supply consumption Max discrete cap loads, Vddq2 = 2.625V All static inputs = Vddq3 or GND 10mA 70mA 100mA Max 2.5V supply consumption Max discrete cap loads, Vddq2 = 3.465V All static inputs = Vddq3 or GND 10mA 280mA 280mA
4
ICS9250-10
Preliminary Product Preview General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 ICS clock will acknowledge each byte one at a time. Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit. Controler (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 5 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit
How to Write:
Controller (Host) Start Bit Address D2(H) Dummy Command Code ICS (Slave/Receiver)
How to Read:
Controller (Host) Start Bit Address D3(H) ICS (Slave/Receiver)
ACK ACK
Dummy Byte Count
ACK Byte Count
ACK
ACK
Byte 0
Byte 0
ACK
Byte 1
ACK
Byte 1
ACK
Byte 2
ACK
Byte 2
ACK
Byte 3
ACK
Byte 3
ACK
Byte 4
ACK
Byte 4
ACK
Byte 5
ACK
Byte 5
ACK
Stop Bit
ACK Stop Bit
Notes:
1. 2. 3. 4. 5.
6.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown. 5
ICS9250-10
Preliminary Product Preview
Byte 5:ICS Reserved Functionality and frequency select register (Default=0)
Bit Bit7 Bit6 Bit5 FS0 (HW) 0 0 0 0 0 0 Bit (4,3,0) 0 0 1 1 1 1 1 1 1 1 Bit2 Bit1
Desctiption ICS RESERVED BIT (Needs to be 0 clock to operate normal) ICS RESERVED BIT (Needs to be 0 clock to operate normal) ICS RESERVED BIT (Needs to be 0 clock to operate normal) Bit (4,3,0) SEL3 (Bit4) 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SEL2 (Bit3) 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SEL1 (Bit0) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPUCLK SDRAM MHz MHz 66.67 70.67 74.66 82.66 63.5 68.67 72.67 88.66 100 106 112 124 95.25 103 109 133 100 106 112 12 4 95.25 103 109 133 100 106 112 124 95.25 103 109 133 3V66 MHz 66.67 70.67 74.67 82.66 63.5 68.67 72.67 88.66 66.67 70.67 74.67 82.66 63.5 68.67 72.67 88.66 PCICLK MHz 33.33 35.33 37.33 41.33 31.75 34.33 36.33 44.33 33.33 35.33 37.33 41.33 31.75 34.33 36.33 44.33
PWD 0 0 0
XXXX Note 1
Not used (Needs to be 1 for normal clock operation) Not used (Needs to be 1 for normal clock operation)
1 1
Note1: Default at power-up will be for latched logic inputs to define frequency, as diplayed by Bit 3.
6
ICS9250-10
Preliminary Product Preview
Byte 0: Control Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 26 25 49 Pin# Name Reserved Reserved Reserved Reserved SpreadSpectrum (1=On/0=Off) 48MHz 1 48MHz 0 CPUCLK2 PWD 0 0 0 1 1 1 1 1 Description (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive)
Byte 1: Control Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin# 36 37 39 40 42 43 45 46
Name SDRAM7 SDRAM6 SDRAM5 SDRAM4 SDRAM3 SDRAM2 SDRAM1 SDRAM0
PWD 1 1 1 1 1 1 1 1
Description (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive)
Byte 2: Control Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Notes:
Pin# 20 19 18 16 15 13 12 -
Name PCICLK7 PCICLK6 PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 Reserved
PWD 1 1 1 1 1 1 1 0
Description (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive)
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation. 2. PWD = Power on Default
7
ICS9250-10
Preliminary Product Preview
Byte 3: Reserved Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin# -
Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
PWD 0 0 0 0 0 0 0 0
Description (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive)
Byte 4: Reserved Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin# -
Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
PWD 0 0 0 0 0 0 0 0
Description (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive)
Notes: 1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation. 2. PWD = Power on Default 8
ICS9250-10
Preliminary Product Preview
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . 4.6 V I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 3.6V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . 0C to +70C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +5%, VDDL=2.5 V+ 5%(unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Input Low Current Operating Supply Current Power Down Supply Current Input frequency Pin Inductance Input Capacitance1 SYMBOL VIH VIL IIH IIL1 IIL2 IDD3.3OP IDD3.3PD Fi Lpin CIN Cout CINX Ttrans Ts TSTAB tPZH,tPZH tPLZ,tPZH CONDITIONS MIN 2 VSS-0.3 -5 -5 -200 TYP MAX UNITS VDD+0.3 V 0.8 V A 5 A A 100 mA 600 A MHz nH pF pF pF mS mS mS nS nS
VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors CL = 0 pF; Select @ 66M CL = 0 pF; With input address to Vdd or GND VDD = 3.3 V; Logic Inputs Out put pin capacitance X1 & X2 pins To 1st crossing of target Freq. From 1st crossing to 1% target Freq. From VDD = 3.3 V to 1% target Freq. output enable delay (all outputs) output disable delay (all outputs)
2.0 -100 60 400 14.318
7 5 6 45 3 3 1 1 3 10 10
27
Transition Time Settling Time Delay
1 1
1
Clk Stabilization1
Guarenteed by design, not 100% tested in production.
9
ICS9250-10
Preliminary Product Preview
Electrical Characteristics - CPU
TA = 0 - 70C, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
SYMBOL RDSP2B1 RDSN2B1 VOH2B VOL2B IOH2B IOL2B tr2B1 tf2B1 dt2B1 tsk2B1 tjcyc-cyc1 VO = VDD*(0.5)
CONDITIONS VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA VOH @MIN= 1.0V , VOH@ MAX= 2.375V VOL @MIN= 1.2V , VOL@ MAX= 0.3V VOL = 0.4 V, VOH = 2.0 V VOH = 0.4 V, VOL = 2.0 V VT = 1.25 V VT = 1.25 V VT = 1.25 V
MIN 13.5 13.5 2 -27 27 0.4 0.4 45
TYP
MAX UNITS 45 45 0.4 -27 30 1.6 1.6 V V mA mA ns ns % ps ps
50
55 175 250
Guarenteed by design, not 100% tested in production.
Electrical Characteristics - 3V66
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
SYMBOL RDSP1 RDSN1 VOH1 VOL1 IOH1 IOL1 tr11 tf1
1 1 1 1 1
CONDITIONS VO = VDD*(0.5)
MIN 12
TYP
MAX UNITS 55 55 0.55 -33 38 2 2 55 175 500 V V mA mA ns ns % ps ps
VO = VDD*(0.5) 12 IOH = -1 mA 2.4 IOL = 1 mA VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V -33 VOL@ MIN = 1.95 V, VOL@ MAX= 0.4 30 VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V 0.5 0.5 45
dt1
tsk1 tjcyc-cyc
Guarenteed by design, not 100% tested in production.
10
ICS9250-10
Preliminary Product Preview
Electrical Characteristics - IOAPIC
TA = 0 - 70C;VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Jitter Skew
1
SYMBOL RDSP4B1 RDSN4B1 VOH4\B VOL4B IOH4B IOL4B tr4B1 tf4B1 dt4B1 tjcyc-cyc Tsk41 VO = VDD*(0.5)
CONDITIONS VO = VDD*(0.5) IOH = -5.5 mA IOL = 9.0 mA VOH@ min = 1.0 V, VOH@ MAX = 2.375 V VOL@ MIN = 1.2 V, VOL@ MAX= 0.3V VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V VT = 1.25 V
MIN 9 9 2 -27 27 0.4 0.4 45
TYP
MAX UNITS 30 30 0.4 -27 30 1.6 1.6 55 500 250 V V mA mA ns ns % ps ps
Guarenteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 - 30 pF (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
SYMBOL RDSP3 RDSN3 VOH3 VOL3 IOH3 IOL3 Tr31 Tf3 Dt3
1 1 1 1 1
CONDITIONS VO = VDD*(0.5) VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA VOH @MIN= 2.0 V, VOH@ MAX=3.135 V VOL@ MIN= 1.0 V, VOL@ MAX=0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 10 10 2.4 -54 54 0.4 0.4 45
TYP
MAX UNITS 24 24 0.4 -46 53 1.6 1.6 55 250 250 V V mA mA ns ns % ps ps
Tsk3 tj cyc-cyc
Guarenteed by design, not 100% tested in production.
11
ICS9250-10
Preliminary Product Preview
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
SYMBOL RDSP1 RDSN1 VOH1 VOL1 IOH1 IOL1 tr11 tf1
1 1 1 1 1
CONDITIONS VO = VDD*(0.5)
MIN 12
TYP
MAX UNITS 55 55 0.55 -33 38 2 2 55 500 500 V V mA mA ns ns % ps ps
VO = VDD*(0.5) 12 IOH = -1 mA 2.4 IOL = 1 mA VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V -33 VOL@ MIN = 1.95 V, VOL@ MAX= 0.4 30 VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V 0.5 0.5 45
dt1
tsk1 tjcyc-cyc
Guarenteed by design, not 100% tested in production.
Electrical Characteristics - REF, 48MHz_0 (Pin 25)
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 -20 pF (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Jitter Skew
1
SYMBOL RDSP5 RDSN5 VOH5 VOL5 IOH5 IOL5 tr51 tf5
1 1 1 1
CONDITIONS VO = VDD*(0.5) VO = VDD*(0.5) IOH = 1 mA IOL = -1 mA VOH @MIN=1 V, VOH@MAX= 3.135 V VOL@MIN=1.95 V, VOL@MIN=0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V; Fixed Clocks VT = 1.5 V; Ref Clocks VT = 1.5 V
MIN 20 20 2.4 -29 29
TYP
MAX UNITS 60 60 0.4 -23 27 V V mA mA ns ns % ps ps ps
1.8 1.7 45
4 4 55 500 1000 250
dt5
tjcyc-cyc1 tjcyc-cyc1 Tsk
Guarenteed by design, not 100% tested in production.
12
ICS9250-10
Preliminary Product Preview
Electrical Characteristics - 48MHz_1 (Pin 26)
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 - 30 pF (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
SYMBOL RDSP3 RDSN3 VOH3 VOL3 IOH3 IOL3 Tr31 Tf3 Dt3
1 1 1 1
CONDITIONS VO = VDD*(0.5) VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA VOH @MIN= 2.0 V, VOH@ MAX=3.135 V VOL@ MIN= 1.0 V, VOL@ MAX=0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 10 10 2.4 -54 54 0.4 0.4 45
TYP
MAX UNITS 24 24 0.4 -46 53 1.6 1.6 55 250 250 V V mA mA ns ns % ps ps
Tsk31 tj cyc-cyc
Guarenteed by design, not 100% tested in production.
13
ICS9250-10
Preliminary Product Preview
Group Offset Waveforms
Group Skews at Common Transition Edges: (CPU = 66MHz)
CPU & IOAPIC load (lumped) = 20pf; PCI, SDRAM, 3V66 LOAD (LUMPED) = 30pf. GROUP SYMBOL CONDITIONS MIN CPU @ 1.25V, 3V66 @ 1.5V 0 CPU to 3V66 SCPU1-3V66 (Note: 180 offset between CPU & 66MHz CPU @ 1.25V, SDRAM @ 1.5V 0 CPU to SDRAM SCPU2-SDRAM (Note: 180 offset between CPU & 66MHz 1.5 3V66 to PCI S3V66-PCI 3V66 @ 1.5V, PCI @ 1.5V IOAPIC to PCI SIOAPIC-PCI IOAPIC @ 1.25V, PCI @1.5V 0
1
TYP
MAX UNITS 500 500 4 500 ps ps ns ps
Guarenteed by design, not 100% tested in production.
Group Skews at Common Transition Edges: (CPU = 100MHz)
CPU & IOAPIC load (lumped) = 20pf; PCI, SDRAM, 3V66 LOAD (LUMPED) = 30pf. GROUP SYMBOL CONDITIONS MIN CPU @ 1.25V, 3V66 @ 1.5V CPU to 3V66 SCPU1-3V66 0 (Note: 180 offset between CPU & 100MHz CPU @ 1.25V, SDRAM @ 1.5V CPU to SDRAM SCPU2-SDRAM 0 (Note: 180 offset between CPU & 100MHz 3V66 to PCI S3V66-PCI 3V66 @ 1.5V, PCI @ 1.5V 1.5 IOAPIC to PCI SIOAPIC-PCI IOAPIC @ 1.25V, PCI @1.5V 0
1
TYP
MAX UNITS 500 500 4 500 ps ps ns ps
Guarenteed by design, not 100% tested in production.
14
ICS9250-10
Preliminary Product Preview
General Layout Precautions: 1) Use a ground plane on the top layer of the PCB in all areas not used by traces. 2) Make all power traces and vias as wide as possible to lower inductance.
Notes: 1) All clock outputs should have series terminating resistor. Not shown in all places to improve readibility of diagram. 2) 47 ohm / 56pf RC termination should be used on all over 50MHz outputs. 3) Optional crystal load capacitors are recommended.
Capacitor Values: C1, C2 : Crystal load values determined by user C3 : 100pF ceramic All unmarked capacitors are 0.01F ceramic
Connections to VDD:
15
ICS9250-10
Preliminary Product Preview
SSOP Package
SYMBOL A A1 A2 B C D E e H h L N COMMON DIMENSIONS MIN. NOM. MAX. .095 .101 .110 .008 .012 .016 .088 .090 .092 .008 .010 .0135 .005 .006 .0085 See Variations .292 .296 .299 0.025 BSC .400 .406 .410 .010 .013 .016 .024 .032 .040 See Variations 0 5 8 .085 .093 .100 VARIATIONS AC AD MIN. .620 .720 D NOM. .625 .725 N MAX. .630 .730 48 56
X
Ordering Information
ICS9250yF-10
Example:
ICS XXXX y F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
16
PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.

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